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Preliminary Technical Data
J1 – MINI USB ‘B’ CONNECTOR
This is used to connect the CED1 to the PC for control and data
transfer
J2 – 2-PIN SCREW TERMINAL POWER CONNECTOR
This connector is used when powering the CED board with a
lab supply. Care must be taken to ensure the external supply is
connected with the correct polarity.
J4 – DC POWER CONNECTOR
When using the CED1 with the supplied power supply, the DC
plug should be connected here. The polarity for this connector
is centre positive.
J6 – FPGA JTAG CONNECTOR
This can be used with Altera SignalTap Logic Analyzer and
appropriate hardware to assist with FPGA development and
debug.
J8, 9, 10 – 3× 90-WAY BLACKFIN EZ-KIT
CONNECTORS
These three connectors bring across most of the peripheral
signals from the Blackfin Ez-Kit directly into the FPGA where
Table 2. 96-way connector pin-out
EVAL-CED1Z
they can be used directly or rerouted to the other connectors.
Additional processor or microcontroller boards could be
designed and connected here if the user wished to add a
processor to the design. See the Blackfin Ez-Kit manual for
details of these connectors.
J3 – 96-WAY DIN41612 CONNECTOR
This connector has traditionally appeared on most precision
ADC evaluation boards. It contains SPI, SPORT and Parallel
signals as well as programmable digital and 5 separate analog
power supplies. Pin out for this connector is shown in Table 2.
Figure 4. 96-way connector pin locations
Pin Num
A1
B1
C1
A2
B2
C2
A3
B3
C3
A4, B4, C4
A5
B5
Pin Name
SPORT_DT1PRI/
SPI_MOSI/PAR_D16
GPIO3/TMR1/
PPI_FS1
SPORT_DR1PRI/
SPI_MISO/PAR_D19
SPORT_TFS1/
SPI_SEL0/PAR_D17
PAR_D0
SPORT_RFS1/
SPI_SEL1/PAR_D20
SPORT_TSCLK1/
SPI_CLK/PAR_D18
PAR_D1
SPORT_RSCLK1/
SPI_CLK/PAR_D21
DGND
SPORT_DT0PRI/
SPI_SEL7
PAR_D2
Description
Sport1 Data Transmit Primary. SPI Master Out, Slave In data line. Parallel Data bit 16.
General Purpose I/O bit 3. Timer 1. Parallel Peripheral Interface Frame Sync 1.
Sport 1 Data Receive Primary. SPI Master In, Slave Out data line. Parallel Data bit 19.
Sport 1 Transmit Frame Sync. SPI Peripheral Chip Select 0. Parallel Data bit 17.
Parallel Data bit 0 (LSb)
Sport 1 Receive Frame Sync. SPI Peripheral Chip Select 1. Parallel Data bit 20.
Sport 1 Transmit Serial Clock. SPI Clock. Parallel Data bit 18.
Parallel Data bit 1.
Sport 1 Receive Clock. SPI Clock. Parallel Data bit 21.
Digital Ground
Sport 0 Data Transmit Primary. SPI Peripheral Chip Select 7
Parallel Data bit 2
Rev. PrA | Page 5 of 24
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